This invention relates to improved EPROM structures and the method of manufacturing the structures with CMOS and BICMOS technologies that utilize lightly doped drain extensions.
The prior art CMOS and BICMOS device structures often consist of an N type lightly doped drain (Nldd) which is used to grade the drain to body doping. This grading is necessary for reliability purposes. Without the grading, the drain to body electric field is large enough to generate an abundance of hot electrons. Hot electrons eventually lead to threshold voltage shifts, drive current degradation, sub-threshold voltage degradation and transconductance degradation. Any or all of these parametric shifts may be sufficient to lead to circuit failures over the life of the circuit. Hence reliability is compromised.
Attempts have been made to solve this problem. U.S. Pat. No. 4,970,565 dated Nov. 13, 1990, describes a method of building a sealed charged storage structure in a memory cell for an EPROM device which is totally sealed from ultraviolet light by a conductive cover without openings therein for leads to the cell""s drain, source and gate. Electrical communication with the source is provided by direct contact with the conductive cover. Access to the drain and floating gate is provided by buried N+ implants, buried N+ layers or N wells crossing underneath the sides of the cover. The memory cell has a single poly floating gate rather than a stacked floating gate/control gate combination. The buried N+ implant or N well serves as the control gate and is capacitively coupled to the floating gate via a thin oxide layer in a coupling area.
U.S. Pat. No. 5,307,312 dated Apr. 26, 1994 describes a process for obtaining an N channel single polysilicon level EPROM cell. The process provides for the simultaneous N+ type implantation of areas of a semiconductor substrate of type P for the formation of a control gate and of highly doped regions of source and drain, defining a channel region. After oxide growth there is executed the deposition and the definition of a polysilicon layer, one region of which constitutes a floating gate above the control gate and the channel region and partially superimposed over the regions of source and drain.
U.S. Pat. No. 5,470,771 dated Nov. 28, 1995, describes a method of manufacturing a floating gate memory device. A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.
Finally, U.S. Pat. No. 5,479,367 dated Dec. 26, 1995 describes an N channel single polysilicon level EPROM cell. The process provides for the simultaneous N+ type implantation of areas of a semiconductor substrate of type P for the formation of a control gate and of highly doped regions of source and drain, defining a channel region. After oxide growth there is executed the deposition and the definition of a polysilicon layer, one region of which constitutes a floating gate above the control gate and the channel region and partially superimposed over the regions of source and drain.
An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the xe2x80x9cfloating gatexe2x80x9d. The remaining side of the capacitor is referred to as the xe2x80x9ccontrol gatexe2x80x9d.
In an unprogrammed state as fabricated, the NMOS transistor has a relatively low threshold voltage (the voltage necessary to turn xe2x80x9conxe2x80x9d the transistor), typically less than 1.0 volts when referenced from the floating gate to ground. In the EPROM structure, there is no direct connection to the floating gate, so the threshold voltage must be referenced to the control gate. Because of capacitive voltage dividing, the threshold voltage is somewhat higher, but still typically less than 2.0 volts when referenced to the control gate. Ignoring parasitic capacitances, the relationship of control gate voltage to floating gate voltage is:
Vfg=Vcg*C1/(C1+C2)
where:
fg=floating gate
cg=control gate
C1=capacitance of the capacitor
C2=gate capacitance of the NMOS transistor
So, with the source and body grounded, the drain biased at some positive voltage (5.0 volts, for example), and the control gate biased greater than the threshold voltage (2.5 volts, for example), the NMOS transistor in an unprogrammed EPROM is in the xe2x80x9conxe2x80x9d state and drain current flows.
To program the EPROM, the bias conditions are set momentarily so that there is a substantial amount of drain current flowing and hot electrons are generated. Typical bias conditions might be 7.0 volts on the drain and 12.0 volts on the control gate. With these bias conditions, a tremendous amount of hot electrons are generated in a typical 5V, 0.5 micron NMOS transistor. With 12.0 volts on the control gate, there might be 10.0 volts or more across the NMOS gate oxide according to the equation given above. This gate oxide potential xe2x80x9cassistsxe2x80x9d the injection of hot electrons (which already have an abundance of energy) through the gate oxide onto the polysilicon gate. Since the polysilicon gate is a floating gate without connections, these electrons are trapped here due to the oxide insulators which encapsulate the polysilicon once the programming event is complete. After xcx9c200 milliseconds (a typical duration of the programming event), the amount of electrons trapped on the floating gate is significant and sufficient to drastically impact the NMOS transistor characteristics. During such programming, it is possible to increase the NMOS transistor threshold voltage to 4.0-10.0 volts. Assuming this new, higher threshold voltage and the same operating bias conditions described above (5.0 volts on the drain and 2.5 volts on the control gate), the NMOS transistor of the EPROM is now in the xe2x80x9coffxe2x80x9d state (negligible drain current flowing). By selectively programming EPROMs on a circuit depending on the circuit behavior, the circuit can be trimmed or fine-tuned to enhance its performance. It should be noted at this time that 200 milliseconds to program a single EPROM can be very costly. On a complex circuit, it is possible that several programming iterations must be performed for each circuit which can significantly added to the probe/test cost. A faster programming EPROM could reduce probe/test cost significantly.
5V CMOS technologies in the 0.5 micron regime generally utilize NMOS architectures which attempt to control hot electron generation. Most popular is the lightly doped drain (NLdd) combined with spacer technology. These precautions are necessary due to reliability concerns. Over the course of a circuit""s active 10 year lifetime, hot electron are continuously being generated at a low level. These hot electrons will degrade the transistor performance (threshold voltage shifts, drive current degradation, sub-threshold slope degradation and transconductance degradation) which can eventually lead to circuit failure. Because of the reliability implications, the NMOS transistor architecture is optimized so that significant hot electron generation is eliminated.
Here is the dilemma: special precautions have been taken to control hot electron generation in the standard NMOS transistor, but excessive hot electron generation is desired in the EPROM""s NMOS transistor for fast, reliable programming. An improved EPROM semiconductor structure invention is formed by the addition of a P type region that augments a P well doping under a NMOS transistor gate. This added P region under the gate is formed by an additional photolithography and an additional implantation process steps. Alternatively, this P region could be formed during other processing steps that are already in the process flow for other reasons (an NPN transistor P Base, for example). The addition of this new P region changes the dopant grading of the drain-body junction which allows for an increase in the generation of hot electrons in the EPROM NMOS transistor. Hence, the EPROM can be programmed faster and/or at a lower voltage. Only the NMOS transistor of the EPROM receives the added P region. The standard NMOS transistor in the remainder of the circuitry does not have the P region so its reliability is not compromised.
The new P type regions do not intersect in the center of the NMOS transistor of the EPROM. This ensures that the threshold voltage in the center of an unprogrammed EPROM remains at a low value of less than 2.0 volts. The existence of the P region along the edges of the device will increase the threshold voltage in these regions.
An enhancement to this design provides a better NMOS layout would have the Nldd regions removed along the edges of the transistor, but present in the center of the device. This would ensure an intersection of the new P type region with N+ and the associated high electric field region.